CD4046 PLL Frequency Multiplier
Use a CMOS phase-locked loop and one feedback divider to multiply a slow reference clock by an integer.
Difficulty: Through-hole. Estimated build time: about 45 minutes. Estimated parts cost: about US$3.00. 4-line bill of materials. Compare supplier offers when available. A textbook phase-locked loop built from the TI CD4046, a single CMOS chip that contains the three pieces you need: a phase comparator, a low-pass loop filter (you add the resistors and capacitor externally), and a voltage-controlled…
Build the reference clock
Start with a 555 in astable mode at about 1 kHz. Wire R_A = 10 kΩ, R_B = 10 kΩ, C_T = 100 nF. The output on pin 3 is your reference square wave.
Drop in the CD4046 and external loop filter
V_DD (pin 16) = 5 V, V_SS (pin 8) = GND. Wire R_1 = 100 kΩ from pin 11 to ground (sets the VCO upper frequency), R_2 = 1 MΩ from pin 12 to ground (sets the lower limit), and C_1 = 1 nF between pins 6 and 7. The loop filter sits between pin 13 (phase comparator out) and pin 9 (VCO_in): a 22 kΩ series resistor and 100 nF cap to ground.
Add a divide-by-N in the feedback path
Pin 4 is VCO_out; pin 3 is signal-in (which expects to see the divided VCO). Wire a 74HC161 (or a CD4040 binary counter) so VCO_out clocks the counter, and the chosen output bit of the counter goes back to pin 3. With N=16 (the Q4 bit) the VCO must run 16 times faster than the reference to lock.
Watch it lock
Power up. On a scope, look at the loop-filter voltage (pin 9). On startup it sweeps up and down as the comparator hunts; within tens of milliseconds it settles at a steady DC level. The VCO output is now 16 kHz — exactly N times the reference. Wiggle the reference and the VCO tracks it. Drop the reference too far and the loop loses lock and the VCO drifts.