74HC393 Dual Binary Counter Clock Divider

Slice a single 555 clock into eight progressively slower frequencies using a dual 4-bit binary counter — the cleanest way to see how a counter chain divides a base frequency by powers of two.

Difficulty: Breadboard. Estimated build time: about 35 minutes. Estimated parts cost: about US$3.60. 8-line bill of materials. Compare supplier offers when available. A clock-divider chain that takes one input frequency and produces eight outputs at /2, /4, /8, /16, /32, /64, /128, /256 of the original.

Set up the clock

Wire a 555 in astable mode running at about 100 Hz: R1 = 10 kOhm, R2 = 6.8 kOhm, C = 1 uF gives roughly that. The output on pin 3 is the master clock that everything downstream divides. (Slower is fine — at 10 Hz you can read the binary count visually; at 1 kHz the slowest output ticks once a second.)

Cascade the 393 halves

Connect the 74HC393: pin 14 to +5 V, pin 7 to GND, pin 1 (1A, first counter clock input) to the 555 output. Pin 2 (1Clr) and pin 12 (2Clr) both to GND so the counters never reset. The first half's last output (1Q3, pin 6) feeds into the second half's clock input (2A, pin 13). The 8 outputs you can tap are 1Q0..1Q3 on pins 3, 4, 5, 6 and 2Q0..2Q3 on pins 11, 10, 9, 8.

Wire eight LEDs

On each of the 8 outputs, put a 330 Ohm resistor and an LED to GND. Power up and watch the binary count race past on the lower bits while the upper bits crawl. The leftmost LED blinks at half the 555 frequency; the rightmost at 1/256 of it. Read across all 8 LEDs at any instant and you see the current count in binary — LSB on the left. This is the same chain that lives inside every RTC, every timer prescaler, and the divide-by-N path of every PLL frequency synthesiser.