Radiation-Hardened FPGA
A programmable chip that a proton can punch straight through without scrambling a single bit of logic — because every storage cell was designed from the transistor up to survive it.
An FPGA (Field-Programmable Gate Array) is a chip that engineers can configure in software to act like any digital circuit — a signal processor, a flight computer, a high-speed communications interface — without custom silicon. In space, this reconfigurability is enormously valuable: the same chip can be reprogrammed in orbit to fix bugs or add capability. The problem is that space is filled with high-energy protons, heavy ions, and electrons that can flip the bits inside ordinary chip memory, corrupting the FPGA's configuration and causing catastrophic failures. A rad-hard FPGA adds a suite of hardening techniques — at the transistor level, the circuit level, and the architecture level — to guarantee that configuration upsets, single-event latchups, and accumulated dose effects cannot corrupt or destroy the device over a mission spanning five to fifteen years.
Radiation damage falls into two categories. Total Ionising Dose (TID) is the cumulative energy deposited by all radiation over the mission; it degrades transistor thresholds and eventually causes parametric failures. Single Event Effects (SEE) are caused by individual particles: a Single Event Upset (SEU) flips a stored bit; a Single Event Latchup (SEL) can latch the chip into a permanent high-current state and destroy it. Three principal hardening approaches are used, often in combination. First, process hardening: Microchip's RTAX antifuse-based FPGAs and RTG4 flash-based FPGAs use intrinsically radiation-resistant cell structures — antifuse connections are permanently blown and cannot be un-blown by a particle; flash cells are engineered to tolerate cumulative ionisation without threshold shift. Second, circuit hardening by design (RHBD): Xilinx's Virtex-5QV uses dual-node interlocking latches where each storage cell has two nodes so far apart that a single particle track cannot strike both; only a simultaneous upset of both nodes can flip the cell, an astronomically unlikely event. Third, Triple Modular Redundancy (TMR): critical logic is triplicated — three copies of every register and voter circuits resolve any single-copy disagreement by majority vote. Some FPGAs implement TMR in hard silicon; others offer it as a synthesis option applied by the designer.
In plain terms
Imagine a whiteboard that you can write any program on, and it stays exactly as you wrote it even when someone shoots tiny invisible bullets through it every few minutes for ten years. Normal computer chips would have their writing smeared all over the place by those bullets. A rad-hard FPGA is a special whiteboard where every letter is locked down so tight that even a cosmic ray particle can't move it.
Also called: rad-hard FPGA, space-grade FPGA, RTG4, Virtex-5QV, RTAX, RHBD FPGA, SEU-immune FPGA.
Why it matters
- A single uncorrected configuration upset in a space FPGA can cause a mission-ending failure: an imaging instrument that produces garbage data, a thruster that fires at the wrong time, or a communication link that goes silent. Rad-hard FPGAs are the foundational layer of fault-tolerant space computing.
- Reconfigurability after launch is a mission multiplier — the James Webb Space Telescope, GPS III, BepiColombo, and dozens of commercial satellites carry Microchip RTAX antifuse FPGAs for functions that had to be finalised before launch, while newer missions use reprogrammable RTG4 or Virtex-5QV parts to allow on-orbit software updates.
- The radiation environment varies dramatically by orbit: LEO inside the ISS orbit is relatively benign; GEO sits inside the outer Van Allen belt where electron fluence is orders of magnitude higher; deep space exposes hardware to galactic cosmic rays with no Earth magnetic-field shielding. Rad-hard FPGAs are characterised across all of these environments so mission designers can confidently select the right part.
- The cost premium over commercial FPGAs (often 100–1,000×) is justified by mission value: a $50,000 rad-hard FPGA protecting a $500 million science spacecraft is good engineering economics.
Where it lives
- James Webb Space Telescope — Microchip RTAX-S antifuse FPGAs in multiple instrument control and data handling boards
- GPS III satellites (Lockheed Martin) — RTAX-S FPGAs for navigation signal processing
- BepiColombo (ESA/JAXA) — Microchip RTAX FPGAs in spacecraft control electronics
- Mars Perseverance rover — AMD/Xilinx Virtex-5 (SIRF) rad-hard FPGAs for computer vision acceleration
- ESA JUICE (Jupiter Icy Moons Explorer, 2023) — Microchip RTG4 FPGAs in science instrument processing chains
- NASA Artemis-1 (2022) — RTG4 FPGAs in Orion spacecraft subsystems
- Galileo navigation satellites — RTAX-S antifuse FPGAs in signal generation payloads
- Iridium NEXT constellation — RTAX devices for crosslink and signal processing
Key numbers
- TID — Virtex-5QV: > 1 Mrad (Si) (Guaranteed by Xilinx/AMD; hardness assurance tested every wafer lot)
- TID — Microchip RTG4: > 125 krad (Si) (Flash-based 65 nm process; immune to configuration upsets at > 103 MeV-cm²/mg LET)
- TID — Microchip RTAX-S: 300 krad functional / 200 krad parametric (Antifuse technology; nonvolatile, one-time programmable)
- SEL immunity — RTAX-S: LET_th > 117 MeV-cm²/mg (No latchup at facility-limit LET; tested at 100°C to bound worst-case)
- SEU rate — RTG4 flip-flops: < 1 × 10⁻¹¹ errors/bit-day (GEO solar minimum environment; below most mission error-budget allocations)
- Logic density — Virtex-5QV: 131,072 logic cells (Highest-density rad-hard FPGA at introduction (2008); 65 nm CMOS)
- Logic density — RTG4: 150 K logic elements (65 nm flash-based process; 24 × 3.125 Gb/s SERDES lanes)
- SEU config immunity — RTG4: No upsets at 103 MeV-cm²/mg (Flash cells hold configuration state with no background scrubbing required)
Surprising facts
- The Virtex-5QV's storage cells are hardened to withstand a total ionising dose of 1 million rad (1 Mrad) — that is the equivalent of sitting next to the core of a nuclear reactor for years. A commercial version of the same chip would fail at about 10–50 krad.
- A single high-energy heavy ion (such as iron from a galactic cosmic ray) can deposit enough charge in a 10 nm gate oxide to flip thousands of bits in a conventional SRAM — in roughly one picosecond. The rad-hard cell must recover full state without any external intervention.
- The Microchip RTAX antifuse FPGAs have accumulated over 33 million device-hours of on-orbit reliability data — a dataset that spans decades of actual space flight across hundreds of programmes, making them among the most thoroughly characterised electronic components ever manufactured.
- Implementing full TMR in an FPGA fabric costs roughly 3× the logic area and more than 3× the power — because the voter circuits add overhead on top of the three-way replication. Yet for a device that must never miscompute in the outer solar system, that overhead is unconditionally worth it.
A short history
The need for radiation-tolerant programmable logic became acute in the 1980s as satellite designers sought the flexibility of gate arrays without the permanent configuration of ASICs. Early approaches used antifuse technology — Actel (now Microchip) introduced the first antifuse FPGA in 1987, and by the mid-1990s space-qualified antifuse devices were flying. The challenge with antifuse parts was one-time programmability: a design flaw caught after launch could not be corrected. Xilinx addressed this with the Virtex-5QV, introduced around 2008 as the first 65 nm rad-hard SRAM FPGA with 1 Mrad TID tolerance and genuine post-launch reprogrammability. Microchip (through Actel/Microsemi acquisitions) responded with the RTG4 in 2015 — a flash-based device that is both reprogrammable and immune to configuration upsets without scrubbing, combining the best properties of both approaches. By the 2020s, Microchip's RT PolarFire at 481 K logic elements and 10 Gb/s SERDES was pushing performance toward what terrestrial data-centre FPGAs achieved a decade earlier, but qualified for deep space.
Sources
- Xilinx/AMD — Virtex-5QV Space-Grade FPGA Data Sheet DS192 (TID, SEU, logic cell specs) (https://www.xilinx.com/publications/prod_mktg/virtex5qv-product-brief.pdf)
- Microchip/Microsemi — RTG4 FPGA Radiation Data, ESA SEFUW 2016 (TID, SEU flip-flop rate, SERDES) (https://indico.esa.int/event/130/contributions/724/attachments/789/966/RTG4_FPGAs_and_SSM_-_ESA_SEFUW_Ken_ONeill_2016-03-16_No_Prop.pdf)
- Microchip Technology — RTAX-S Radiation-Tolerant FPGAs product page (TID, SEU, SEL specs, heritage missions) (https://www.microchip.com/en-us/products/fpgas-and-plds/radiation-tolerant-fpgas/rtax-s)
- NASA NEPP — A Comparison of Radiation-Hard and Radiation-Tolerant FPGAs for Space Applications (JPL internal, 2004) (https://nepp.nasa.gov/docuploads/3C8F70A3-2452-4336-B70CDF1C1B08F805/JPL%20Rad-Tolerant%20FPGAs%20for%20Space%20Applications.pdf)
- Embedded.com — FPGAs Help Pave the Way for Modernised Space Computing (RTG4 flight heritage: Artemis-1, JUICE, SLIM) (https://www.embedded.com/fpgas-help-pave-the-way-for-modernized-space-computing-innovation-ecosystem/)