CMOS Image Sensor

A silicon wafer where each of a hundred million pixels contains its own amplifier, performing correlated double sampling to read out light so faintly it might be a single photon.

A CMOS image sensor converts a two-dimensional spatial pattern of light into a digital image by detecting photons pixel-by-pixel across a silicon array. Each pixel contains a photodiode that absorbs incoming photons and converts them to electrical charge, plus the transistor circuitry to read out that charge as a voltage with low noise. The array is fabricated in standard (or near-standard) CMOS processes, allowing the analog pixel array, column-parallel analog-to-digital converters, digital timing, and image signal processing to be integrated on the same die or bonded wafer stack. The resulting imagers power virtually every consumer camera, medical imaging device, machine-vision system, and scientific instrument that does not require the deep-depletion structures of CCDs or specialised HgCdTe focal-plane arrays.

The dominant pixel architecture is the 4-transistor (4T) active pixel with a pinned photodiode. The pinned photodiode is a p-n junction whose surface is pinned to a fixed potential by a p+ surface layer, suppressing surface dark current (thermally generated electrons not caused by photons). During integration, photons absorbed in the silicon depletion region create electron-hole pairs; electrons accumulate in the photodiode potential well. At readout, the transfer gate (TX) transistor opens briefly, transferring the charge packet from the photodiode to the floating diffusion (FD) node, a small capacitor whose voltage changes by V = Q/C_FD. The conversion gain — the voltage per electron at the FD — is typically 50–200 µV/e⁻; smaller C_FD (achieved through process scaling) gives higher conversion gain and lower read noise. A source follower transistor buffers the FD voltage onto the column readout line; the row-select transistor gates the pixel onto the shared column. Correlated double sampling (CDS) measures the FD voltage twice — once after reset (capturing reset noise) and once after signal transfer — and subtracts them, eliminating kTC reset noise and fixed-pattern noise from threshold variations. Modern stacked BSI (backside-illuminated) sensors flip the wafer so that metal interconnects are on the substrate backside, and light enters the photodiode from the front silicon surface without passing through metal layers, improving quantum efficiency to 50–80% in the visible. In 3D-stacked sensors (Sony Exmor RS), the pixel array wafer and the logic/ADC wafer are bonded face-to-face via copper-copper bonds, allowing the logic layer to be optimised independently.

In plain terms

Imagine a giant grid of buckets in the rain. Each bucket is a pixel. When it rains (light hits), buckets fill with drops (electrons). On a normal camera chip (CCD), all buckets pass their water along a chain to one measuring cup at the edge, which gets slow and noisy. On a CMOS chip, every bucket has its own tiny measuring cup right next to it, so all buckets can be read at the same time and much more quietly.

Also called: APS, active-pixel sensor, CMOS APS, 4T pixel sensor, backside-illuminated CMOS sensor, BSI CMOS.

Why it matters

CMOS image sensors enabled the smartphone camera: a device integrating 10–12 megapixels in a package under 5 mm tall, at a cost below $5, with on-chip ISP, autofocus, and video encoding. CCD technology could not approach this integration level.
Read noise below 2 e⁻ rms in modern stacked sensors enables single-photon counting in consumer devices — a capability previously confined to scientific intensified CCDs costing tens of thousands of dollars.
Scientific imagers based on CMOS (e.g., sCMOS sensors from Hamamatsu and Teledyne) have displaced CCDs in fluorescence microscopy and single-molecule imaging because their column-parallel readout allows both low noise and high frame rate simultaneously, whereas CCDs trade one against the other.
The same pixel architecture developed for cameras is the basis of X-ray flat-panel detectors, charged-particle trackers at CERN (MAPS detectors in ALICE and ATLAS upgrades), and time-of-flight depth sensors in consumer devices.

Where it lives

Sony IMX989 — 1-inch 50 MP BSI stacked CMOS, Xiaomi 12S Ultra and Leica-branded handsets; 3.2 µm pixel pitch, 15,000 e⁻ full-well capacity
Sony IMX661 — 150 MP global-shutter CMOS for machine vision and semiconductor inspection; 3.45 µm pixel
Samsung ISOCELL HP2 — 200 MP CMOS at 0.6 µm pixel pitch (pixel-binning to 12.5 MP in low light), Samsung Galaxy S23 Ultra
Canon EOS R5 sensor — 45 MP full-frame CMOS with dual-gain readout; 4.4 µm pixel, used in professional video and stills
Teledyne e2v Osprey — 150 MP sCMOS for astronomical surveys and Earth observation
Gpixel GMAX3265 — 32 MP global-shutter BSI CMOS for high-speed industrial imaging at 47 fps

Key numbers

Quantum efficiency (BSI, visible): 50–80% (vs 30–50% for frontside-illuminated (FSI); peak near 500–600 nm where silicon absorbs efficiently)
Conversion gain: 50–200 µV/e⁻ (At floating diffusion; higher gain (smaller C_FD) enables lower read noise in small pixels (Fossum & Hondongwa 2014))
Read noise (modern stacked BSI): <2 e⁻ rms (Achieved with column-parallel ADC and correlated double sampling; enables near single-photon detection at room temperature)
Pixel pitch range: 0.6–11 µm (Mobile: 0.6–1.4 µm (pixel-binning required at low light); full-frame consumer: 4–6 µm; scientific: 6–11 µm)
Native ADC resolution: 10–14 bits (Per column or per pixel; 14-bit enables 16,384:1 dynamic range per frame)
Full-well capacity (typical BSI mobile pixel): 2,000–5,000 e⁻ (Sets maximum scene dynamic range per frame; larger pixels have larger full wells)

Surprising facts

A modern 1 µm-pixel CMOS imager has a photodiode with a light-collecting area of one square micrometre — roughly 50× smaller than a red blood cell. At ISO 25,600, this pixel must measure a signal corresponding to perhaps 10–20 electrons reliably, which requires sub-2-electron read noise.
The floating diffusion conversion gain of 200 µV/e⁻ means a single electron changes the node voltage by only 200 microvolts — the equivalent of adjusting a 5 V supply by 0.004%. Column-parallel ADCs with 14-bit resolution must resolve this reliably from every one of several million pixels simultaneously.
Sony's backside-illuminated stacked sensor technology (first introduced in the Exmor RS in 2012) requires bonding two full wafers face-to-face with copper-to-copper interconnects at sub-micrometre alignment tolerance, then thinning the pixel wafer to ~3 µm. The thinned wafer is mechanically fragile enough that it is handled exclusively in cassettes without direct contact.
Eric Fossum invented the active-pixel sensor concept at NASA's Jet Propulsion Laboratory in 1993 originally to make smaller cameras for planetary spacecraft, not consumer products. The technology he transferred to Photobit Corporation (later acquired by Micron, then Aptina, then ON Semiconductor) became the foundation of every smartphone camera sold today.

Open questions

Pixel shrinkage has outrun the diffraction limit of light: Mobile CMOS pixels at 0.6–0.8 µm pitch are smaller than the Airy disk of any realistic camera lens at visible wavelengths (the Rayleigh diffraction limit for a lens at f/1.8 is roughly 1.3 µm for green light). This means individual pixels cannot resolve spatially independent information — adjacent pixels see a blur of the same point-spread function. Manufacturers compensate with pixel-binning, tetracell, and octa-cell readout modes, but the pixel pitch is no longer the resolution-limiting factor in the optical system. The imaging performance is now limited by the optics and by computational demosaicing, not by the silicon.

A short history

Solid-state imaging began with the charge-coupled device (CCD), invented by Willard Boyle and George Smith at Bell Labs in April 1969 — work that earned them the 2009 Nobel Prize in Physics. CCDs dominated scientific and consumer imaging through the 1980s because their charge-transfer readout mechanism achieved very low noise. CMOS transistors were considered too noisy for imaging until Eric Fossum and colleagues at NASA's Jet Propulsion Laboratory, working from 1993 to 1997, demonstrated that on-chip amplification (the active-pixel sensor) and correlated double sampling could reduce CMOS read noise to levels competitive with CCDs, with the major additional benefit of allowing integration of timing, ADC, and signal-processing circuits. Fossum co-founded Photobit Corporation in 1995 to commercialise the technology. Canon produced the first CMOS camera sensor for a consumer product (the D30 DSLR, 2000). Sony's development of the pinned photodiode process improvement and the backside-illuminated (BSI) architecture (Exmor, 2007; Exmor R BSI, 2009) transformed image quality in mobile devices. Sony's stacked BSI sensor (Exmor RS, 2012) bonded the pixel wafer to a logic wafer — the architecture now standard in premium smartphones. By 2020, CMOS sensors had displaced CCDs in virtually all consumer, medical, and most scientific imaging markets.

Sources

Fossum E.R. — 'CMOS Image Sensors: Electronic Camera-On-A-Chip', IEEE Trans. Electron Devices 44(10), 1689–1698 (1997). DOI: 10.1109/16.628824 (https://doi.org/10.1109/16.628824)
Fossum E.R. & Hondongwa D.B. — 'A review of the pinned photodiode for CCD and CMOS image sensors', IEEE J. Electron Devices Society 2(3), 33–43 (2014). DOI: 10.1109/JEDS.2014.2306412 (https://doi.org/10.1109/JEDS.2014.2306412)
Theuwissen A.J.P. — 'Solid-State Imaging with Charge-Coupled Devices' (Kluwer Academic, 1995). ISBN 978-0-7923-3456-9 (https://link.springer.com/book/10.1007/978-94-011-0359-9)
Sony Semiconductor Solutions — CMOS image sensor product portfolio and technology documentation (https://www.sony-semicon.com/en/products/IS/)
Boyle W.S. & Smith G.E. — 'Charge coupled semiconductor devices', Bell Syst. Tech. J. 49(4), 587–593 (1970). DOI: 10.1002/j.1538-7305.1970.tb01790.x (https://doi.org/10.1002/j.1538-7305.1970.tb01790.x)