GaN FET
A GaN power transistor controls current in a power circuit. This guide focuses on the lateral enhancement-mode devices described by EPC, not every GaN RF transistor, cascode or integrated power stage. Gate limits, voltage ratings and drive requirements depend on the exact implementation.
In EPC's described enhancement-mode structure, positive gate bias forms a conducting channel between drain and source; removing that bias restores the blocking region. Reverse conduction uses the channel rather than the silicon-MOSFET-style body diode. The absence of minority-carrier reverse-recovery charge does not eliminate output-capacitance charging, reverse-conduction loss or other switching losses.
In plain terms
Think of a fast valve with a precise handle. Moving it quickly can reduce time spent half-open, but careless control or a poor pipe layout can create other losses and stresses. Speed alone does not guarantee an efficient converter.
Why designers use it
- Reduce switching-related charge in a suitable power-conversion design.
- Explore higher switching frequencies when total loss and thermal limits allow.
- Use a specified enhancement-mode device with an appropriate driver and compact current loops.
Best for
- Suitable high-frequency converters
- Compatible power switching
- Studying switching-loss trade-offs
Key specifications
- Power ratings: Exact device voltage, current and temperature limits (Do not apply a portfolio-wide range to a selected part.)
- Gate drive: Recommended voltage and absolute limits (Threshold voltage is not the recommended fully-on drive voltage.)
- Switching behavior: Charge, capacitance and reverse conduction (Use the chosen device's curves and the actual circuit conditions.)
- Layout: Gate and power-loop inductance (Follow the manufacturer's driver and layout guidance.)
When not to use it
- When the available driver or layout cannot keep gate and power-terminal stresses within the device limits.
- When the required reverse conduction, thermal performance or protection cannot be supported by the complete design.
Common mistakes
- Using a gate voltage intended for a silicon MOSFET without checking the GaN device's limits.
- Treating zero reverse-recovery charge as zero switching loss.
- Assuming all GaN devices share the same gate structure or normally-off behavior.
- Promising a fixed efficiency improvement or switching-frequency range for every converter.
Where you will find it
- EPC AN002 uses EPC2218 curves to illustrate gate drive, on-resistance and capacitance. Its drive discussion applies to the documented EPC implementation, not every GaN product.
- The same note describes a demonstrated 1 MHz buck regulator using EPC 100 V transistors. This is an application example rather than a universal operating frequency or efficiency guarantee.
A short history
EDN's history describes EPC unveiling enhancement-mode GaN-on-silicon power transistors in 2009. EPC's technical note explains one resulting device architecture. Both provide useful context, but manufacturer comparisons are not independent proof of a fixed advantage in every circuit.
Good to know
- No minority-carrier reverse-recovery charge does not mean no capacitance to charge and discharge.
- Dead-time reverse conduction can still dissipate power even without the usual silicon body diode.