PLL
A PLL takes a reference clock at f_REF and produces an output clock at N · f_REF / R (where N and R are integer or fractional dividers), with phase locked to the reference. Examples: Texas Instruments LMK04832 RF clock generator, Analog Devices ADF4356 6.8 GHz fractional-N synthesiser, Si5345 jitter cleaner.
A phase-frequency detector (PFD) compares the reference and the divided VCO output, outputting up/down pulses proportional to the phase error. A charge pump converts the pulses into a current that charges a low-pass filter (the loop filter) producing a control voltage that nudges the VCO frequency. A divider in the feedback path (÷N) sets the multiplication factor. After settling, the loop holds the VCO precisely at N · f_REF, and the output inherits the reference's long-term frequency stability while having any close-in phase noise filtered by the loop bandwidth.
In plain terms
A self-correcting metronome: a knob-tunable buzzer with an ear that listens to a reference tick; whenever the buzzer drifts ahead or behind, the knob is nudged until the buzzer hums in perfect lockstep.
Why designers use it
- Synthesise an arbitrary RF carrier (e.g., 2.4 GHz Wi-Fi channels) from a 40 MHz crystal.
- Generate the GHz-scale CPU and memory clocks inside an SoC from a single low-frequency external reference.
- Recover the embedded clock from a high-speed serial data stream (SerDes, USB, PCIe).
- Clean up jitter on a noisy reference clock by setting a narrow PLL loop bandwidth.
Best for
- Frequency synthesis
- Clock multiply
- Jitter cleaning
Key specifications
- Operating limits: Check the exact manufacturer's datasheet (A family name does not establish voltage, current, temperature or timing limits.)
- Pin assignment: Match the complete part and package code (A similar name or function does not guarantee the same wiring.)
- Mechanical fit: Use the exact package drawing (Check pad layout, dimensions and viewing direction before building.)
When not to use it
- When ultra-fast frequency hopping (sub-µs) is required across a wide range — direct digital synthesis (DDS) is faster than the PLL settling time.
- For sub-Hz reference comparison — the loop filter values become unreasonably large; use a digital phase accumulator instead.
Common mistakes
- Setting loop bandwidth higher than f_REF/10 — the loop becomes unstable and oscillates around the reference frequency.
- Using too narrow a loop filter on a noisy VCO — the loop fails to suppress VCO close-in phase noise, degrading output spectrum.
Where you will find it
- An iPhone 15's modem chip locks an internal PLL to a 19.2 MHz crystal and synthesises any cellular carrier from 700 MHz to 6 GHz on demand: when the phone hands off between 5G NR bands, a fractional-N PLL retunes the VCO in under 50 µs, holding the output's phase noise low enough that the OFDM constellation EVM stays under −40 dB.
- An Intel Core i9 generates its 5.8 GHz turbo clock from a 100 MHz BCLK reference using an on-die LC PLL: the PLL multiplies BCLK by 58, and a power-management unit can change the divider on the fly to step the core clock between idle (0.8 GHz) and turbo (5.8 GHz) within a few microseconds while staying phase-coherent with the rest of the system.
- A 100GBASE-LR4 optical Ethernet transceiver uses a CDR-PLL to recover the bit clock from a 25.78125 Gb/s serial stream: the PLL's narrow bandwidth (~1 MHz) tracks the long-term frequency of the incoming line while filtering high-frequency jitter, and the recovered clock samples each bit at its eye centre — without it, the receiver could not distinguish 1s from 0s after the signal walks 10 km of fibre.
A short history
A phase-locked loop compares a reference signal with feedback from an oscillator. A filtered error signal adjusts the oscillator toward a locked relationship with the reference. Adding a divider in the feedback path allows frequency synthesis, while other PLL arrangements can help recover or condition clock signals.