USB Transcvr
Drives the D+/D− differential pair with the standard's voltage and slew-rate envelopes (3.3 V single-ended for low/full speed; 400 mV differential at 480 Mb/s for high speed); inserts NRZI encoding and bit-stuffing; and selects 1.5 kΩ pull-up resistor on D+ (full speed) or D− (low speed) so the host detects the device's correct speed.
Push-pull line drivers with controlled slew rates (10–25 ns rise/fall for full speed) drive the cable's 90 Ω differential impedance through 22–33 Ω series resistors. A high-speed mode switches to a 17.78 mA constant-current driver into 45 Ω terminations for 480 Mb/s eye-mask compliance. Receiver-side hysteresis and squelch detectors filter out noise during disconnect; a SOF (start-of-frame) detector synchronises the PHY's PLL to the host's clock.
In plain terms
Like a hand on a clutch pedal — the controller decides which gear to be in, and the PHY actually engages the impedance, slew rate, and timing that lets the cable carry power smoothly to the bus.
Why designers use it
- Universal interconnect — every laptop, phone, and instrument exposes USB, so the PHY's compliance to USB-IF eye masks is non-negotiable.
- Speed scalability — the same chip family supports low (1.5 Mb/s), full (12 Mb/s), and high (480 Mb/s) speed with seamless host-side renegotiation.
- Hot-plug robustness — the PHY's input ESD diodes survive ±15 kV human-body discharges from users plugging cables into a USB-A port in winter.
Best for
- External PHY
- USB OTG
- Industrial bridges
Key specifications
- USB speeds: 1.5 / 12 / 480 Mb/s (LS / FS / HS)
- Differential signalling: D+/D− at 3.3 V
- Charging detection: BC1.2 SDP / CDP / DCP
- ESD: ±8 kV HBM
- Supply: 3.3 V or 5 V
When not to use it
- When the MCU already integrates a USB PHY — most modern MCUs ship with the PHY on-die; an external chip wastes board space and a UTMI/ULPI interface.
- For SuperSpeed (5/10/20 Gb/s) — those need a redriver/retimer plus a separate USB 3.x PHY, not a USB 2.0 transceiver.
Common mistakes
- Routing D+ and D− as plain single-ended traces without 90 Ω differential impedance control — the eye collapses at 480 Mb/s and the host marks the device 'unrecognised' on every plug-in.
- Forgetting the 1.5 kΩ pull-up on D+ (or letting the PHY default to its low-speed value of 1.5 kΩ on D−) — the host enumerates the device at the wrong speed and the bandwidth never appears.
Where you will find it
- A Saleae Logic 8 logic analyser uses a Microchip USB3320 high-speed PHY between its FPGA and the USB-B receptacle: the chip's ULPI back-end keeps the FPGA's pin count low, while its on-chip squelch detector sleeps the analog block when the PC closes the analyzer software.
- Texas Instruments' TPS65987DDH USB Type-C and PD controller integrates a TUSB1042 USB 2.0 PHY beside its Power Delivery state machine: the integrated PHY shaves a chip off Apple's USB-C charger reference design and meets 480 Mb/s eye-mask compliance without an external retimer.
- An older Cypress CY7C68013A FX2LP firmware-loadable USB device on a Sigrok-supported logic analyser uses an internal USB 2.0 transceiver to push 480 Mb/s: the chip's serial interface engine converts the PHY's bit stream into 8-bit-wide GPIF transactions that the FPGA reads at 48 MHz.
A short history
A USB 2.0 transceiver drives and receives signals on the D+ and D- pair. Its electrical behaviour depends on the operating speed, including the signalling levels and termination. It forms the physical interface for communication between a host and a peripheral; newer USB modes can use additional signal paths.
Good to know
- USB 2.0 high-speed (480 Mb/s) was a tough crossover — the data rate is high enough to need controlled-impedance traces but low enough that most cheap cables still work.
- BC1.2 charging detection lets a phone identify whether the upstream port is a host (500 mA), a charging port (1.5 A), or a wall adapter (any current up to the cable rating).
- USB 3.x split into two lanes — USB 2 high-speed and USB 3 SuperSpeed — both running over the same connector but with separate transceivers inside.