SerDes
A SerDes converts an N-bit-wide parallel word into a serial bitstream at N× the bit rate, then recovers it on the receiving side. Examples include the TI TLK2711 (1.6–2.7 Gbit/s), the Maxim MAX24287 (Ethernet PHY), and integrated 25–56 Gbit/s SerDes blocks inside FPGAs and switch ASICs.
On the transmit side, an 8b/10b or 64b/66b encoder stuffs the parallel data with framing bits, then a parallel-to-serial shift register clocked at line rate fires the bits onto a differential pair driven by an LVDS or CML output stage. On the receive side, a clock-data-recovery (CDR) loop locks onto the embedded edge transitions, samples the bits, and feeds a serial-to-parallel shift register that re-creates the parallel word at the slower system clock.
In plain terms
A bottling plant's narrow conveyor: bottles arrive eight-abreast on the production line, get squeezed into a single-file queue for shipping, then fan back out at the supermarket.
Why designers use it
- Carry many bits over a single backplane lane, dramatically reducing connector pin-count and PCB layer count.
- Build the physical layer of high-speed protocols like PCIe, USB 3, SATA, 10G Ethernet, and HDMI.
- Cross long board distances using equalised differential signalling instead of slow parallel busses.
- Reach across optical transceivers — the SerDes drives the laser modulator and recovers the photodiode current on receive.
Best for
- Backplane links
- Optical TXs
- Chip-to-chip
Key specifications
- Operating limits: Check the exact manufacturer's datasheet (A family name does not establish voltage, current, temperature or timing limits.)
- Pin assignment: Match the complete part and package code (A similar name or function does not guarantee the same wiring.)
- Mechanical fit: Use the exact package drawing (Check pad layout, dimensions and viewing direction before building.)
When not to use it
- For short, slow chip-to-chip links inside one PCB — a parallel SPI or LVDS bus is cheaper and consumes far less power.
- For low-cost designs with no clock-distribution discipline — SerDes CDRs need clean reference clocks (low jitter) to lock reliably above 5 Gbit/s.
Common mistakes
- Routing a 5 Gbit/s differential pair across multiple PCB layer transitions without back-drilled vias, introducing return-path discontinuities that close the eye.
- Using a generic crystal oscillator for the SerDes reference instead of a low-jitter LVPECL clock IC — the recovered eye degrades by 50 % and the link won't lock at full rate.
Where you will find it
- A 100 GbE switch ASIC's PHY layer integrates 32 channels of 25 Gbit/s SerDes feeding QSFP28 optical modules: each SerDes serialises a 32-bit datapath at 781.25 MHz internal clock into a 25 Gbit/s serial stream, multiplying inter-chip bandwidth without adding pins.
- A medical CT-scanner gantry uses TLK2711 SerDes pairs to send detector data across the rotating slip-ring interface: the single 2.5 Gbit/s differential pair replaces a 24-conductor parallel bus that wouldn't have survived a year of slip-ring contact wear.
- An automotive surround-view camera system uses a Maxim GMSL SerDes to send 1080p60 video from each of four cameras over a single coax cable to the head-unit ECU: the SerDes embeds video, control, and power on one wire, replacing the LVDS-plus-CAN-plus-power harness that earlier systems needed.
A short history
SerDes (serializer/deserializer) circuitry converts data between parallel and serial forms. The serializer block takes multiple simultaneous digital signals and outputs a sequence of logic levels on one or a few conductors, while the deserializer converts that sequence back into parallel signals. This approach can minimize the number of I/O pins and interconnects needed for high speed communications between devices.