LVDS Driver
An LVDS driver outputs a complementary pair of signals on two wires terminated by a 100 Ω resistor at the receiver, with a swing of ~350 mV around a 1.2 V common mode. The DS90LV047 quad LVDS driver and DS90LV048 quad LVDS receiver are textbook National (now TI) parts; modern integrated SerDes blocks include LVDS as a low-rate option below 1 Gbit/s.
The driver's output stage is a constant-current source (~3.5 mA) steered by a CMOS switch into one of the two output lines, and the same current returns through the receiver-side termination resistor. The receiver uses a high-CMRR differential amplifier to extract the polarity of the 350 mV across the 100 Ω termination, ignoring the 1.2 V common-mode level. Because the current loop is closed, common-mode noise picked up on the cable cancels out.
In plain terms
A canoe paddler whose two oars push opposite directions in synchrony: the boat moves forward smoothly, but observers on shore can't tell which oar is doing what — only the difference matters.
Why designers use it
- Drive a flat-panel LCD's RSDS or LVDS link from a graphics controller without the EMI of a parallel TTL bus.
- Distribute clocks across a backplane with low skew and jitter.
- Carry data between two cards over a 5 m cable at 400 Mbit/s with negligible radiated emissions.
- Form the physical layer of legacy SCSI, SerDes-lite links, and FPGA-to-FPGA fabric extensions.
Best for
- LCD links
- Clock distrib
- Cable extensions
Key specifications
- Operating limits: Check the exact manufacturer's datasheet (A family name does not establish voltage, current, temperature or timing limits.)
- Pin assignment: Match the complete part and package code (A similar name or function does not guarantee the same wiring.)
- Mechanical fit: Use the exact package drawing (Check pad layout, dimensions and viewing direction before building.)
When not to use it
- For multi-Gbit/s links — LVDS tops out around 1 Gbit/s; use CML or PAM4 SerDes for higher rates.
- On long uncontrolled cables (>10 m) where common-mode immunity isn't enough — use M-LVDS or RS-485 with explicit common-mode budget.
Common mistakes
- Forgetting the 100 Ω termination at the receiver — the driver's current source has nowhere to go and the lines float to the rails, looking like a stuck DC offset.
- Routing the differential pair on impedance-uncontrolled traces — 50 Ω single-ended dominates and the eye closes from reflections.
Where you will find it
- A laptop's hinge cable uses a 6-bit LVDS link from the GPU to the LCD panel: three differential pairs carry 18-bit colour at 60 Hz across the hinge, and the receiver-side 100 Ω terminations sit inside the panel's timing controller — a topology that became standard in every laptop from 2000 to roughly 2017.
- A medical CT-scanner's distributed acquisition card uses DS90LV047 drivers to fan out a 100 MHz clock to 16 slave detector cards: LVDS's tight skew (under 100 ps card-to-card) keeps the X-ray sample timing aligned to a single rotation tick.
- A high-speed industrial camera uses an LVDS Camera Link bus to deliver 1.2 Gbit/s of image data from the camera head to the frame-grabber over a 7 m cable: the differential signalling and 1.2 V common mode shrug off welder-EMI in the factory while the cable's 100 Ω controlled impedance preserves the eye.
A short history
An LVDS driver steers current through a differential connection to represent logic states. The receiver responds to the voltage difference between the conductors, rather than either conductor alone. The small signal swing can reduce switching noise, while differential reception helps reject common-mode interference within the receiver's operating limits.