Latch
A latch holds a logic level on its output until told to update. The 74HC373 is an 8-bit transparent D-latch (output follows input while LE is high, holds when LE drops); the 74HC573 is the same with non-inverted enables for cleaner address bus de-multiplexing.
Inside each cell, two cross-coupled inverters form a bistable element. A pair of pass-transistors feed the input D into the loop while the latch-enable LE is high, and break the input path when LE is low — freezing the bistable in whatever state the input was driving. Unlike an edge-triggered flip-flop, a latch is transparent (output tracks input) while LE is asserted.
In plain terms
A camera shutter held open with a foot pedal: while you're pressing, the film records whatever's in the frame; release the pedal and the last image is locked in.
Why designers use it
- De-multiplex an Intel-style multiplexed address/data bus: latch the lower 8 address bits when ALE pulses, presenting them as A[7:0] until the next cycle.
- Capture an asynchronous strobe pulse from a sensor into a register the CPU can read at leisure.
- Hold a port-expander byte stable while a peripheral consumes it.
- Build a low-cost data buffer between two domains where the timing relationship is well-controlled.
Best for
- Address latch
- Strobe capture
- Port hold
Key specifications
- Operating limits: Check the exact manufacturer's datasheet (A family name does not establish voltage, current, temperature or timing limits.)
- Pin assignment: Match the complete part and package code (A similar name or function does not guarantee the same wiring.)
- Mechanical fit: Use the exact package drawing (Check pad layout, dimensions and viewing direction before building.)
When not to use it
- In synchronous logic where every storage element should be edge-triggered — latches break static-timing analysis if mixed with flip-flops carelessly.
- For high-speed pipelines — a flip-flop's defined edge captures cleaner data than a level-sensitive latch's transparent window.
Common mistakes
- Forgetting that the latch is transparent while LE is high, propagating glitches on D directly to the output — designers expecting flip-flop behaviour see unintended pulse trains.
- Mixing latch-based and flip-flop-based clocking domains in an FPGA without dedicated 'latch-up' synthesis attributes, breaking timing closure unpredictably.
Where you will find it
- An 8051 microcontroller's external memory port uses a 74HC573 to capture A[7:0] off the multiplexed AD0–AD7 bus when the ALE signal pulses: the latch holds those eight address bits stable while the CPU drives data on the same pins, a topology Intel introduced in 1980 that survives in cost-sensitive embedded designs today.
- A vintage dot-matrix printer's character-generator board uses 74LS373 latches to capture the row pattern from ROM during a scan cycle: each latch holds one row while subsequent rows are fetched, building up the printable character in time-multiplexed fashion.
- A laboratory-instrument's GPIB interface uses a 74HC373 to hold a measurement byte stable on the bus during the IEEE-488 handshake: the talker writes to the latch, asserts DAV, and the listener reads from the latch's output — the latch decouples the controller's internal clock from the bus's asynchronous handshake timing.
A short history
A latch stores a logic state. In a typical active-HIGH D latch, the output follows the data input while enable is HIGH, then retains the last value when enable goes LOW. This transparency distinguishes it from an edge-triggered flip-flop, which samples at a clock transition.