OR Gate
An OR gate produces logic-1 when any input is at logic-1, and 0 only when all inputs are 0. The 74HC32 is the canonical CMOS quad 2-input OR; wider variants combine 3, 4, or 8 inputs.
In CMOS, an OR is built as a NOR followed by an inverter. Two NMOS transistors in parallel pull the NOR output low whenever any input is high, while two PMOS in series pull it high only when all inputs are low; the trailing inverter flips that to OR polarity. The parallel NMOS gives the OR a fast 0→1 transition.
In plain terms
A house with two doorbells, one front and one back: ringing either bell makes the chime sound. Both ringing at once still makes one chime — the OR doesn't count; it just notices.
Why designers use it
- Combine independent fault flags into a single 'fault present' line that wakes a supervisor.
- Build sum-of-products logic by OR-ing the outputs of several AND minterms.
- Wire-OR multiple interrupt sources onto a single MCU IRQ pin without a microcontroller's internal logic.
- Construct an 'either/or' enable that responds to either a manual button OR a remote command.
Best for
- Fault aggregation
- Interrupt OR
- SOP minterms
Key specifications
- Logic family: 74HC, 74LV, 74AUP, 74AHCT
- Supply: 1.65 V – 5.5 V
- Propagation delay: 2 ns – 10 ns
- Drive strength: 4 – 24 mA
When not to use it
- For multi-source bus arbitration where you need to know which source asserted — use a priority encoder instead.
- Inside a synchronous design that already has an FPGA available — OR is a free LUT term and a discrete IC adds latency.
Common mistakes
- Floating an unused input — the OR identity is 0, so unused inputs must be tied to GND, not left to drift.
- Using an OR to merge two open-drain busses — open-drain wires already form a wired-AND with pull-up; an OR gate fights them and breaks the bus.
Where you will find it
- In an illustrative logic exercise, two independent request signals feed an OR function so either request can assert the output.
- A Boolean truth table alone does not establish fault tolerance or safety certification. Do not use a basic gate example as an emergency-stop design.
A short history
An OR gate is a digital logic circuit with two or more inputs and one output. The output becomes high when any one or more of its inputs are high, and goes low only when all inputs are low. This any-or-all behavior makes it useful for building circuits where several independent conditions should each be able to trigger the same output response.
Good to know
- An OR gate outputs high when any input is high — the boolean union. Cascade them with NOTs and you've built every digital function ever needed.
- A 74HC32 quad 2-input OR is the textbook 'sum bit' of a half-adder when paired with an AND gate (carry).
- Wired-OR is a common trick: tie open-drain outputs together, pull-up to Vcc, and any output going low pulls the bus low — no gate needed.