AND Gate
An AND gate produces a logic-1 output if and only if every input is also at logic-1; if any input is 0, the output is 0. The 74HC08 is the canonical CMOS quad 2-input AND, and 3- and 4-input versions exist for combining more conditions.
In CMOS, an AND gate is built as a NAND followed by an inverter — two PMOS transistors in parallel pull the NAND output high only when both inputs are 0, and two NMOS in series pull it low only when both are 1; the inverter restores the AND polarity. The series NMOS chain is the source of the AND's slightly slower propagation versus a NAND.
In plain terms
Two padlocks on the same door: the door opens only when both locks are unlocked. If even one is still locked, the door stays shut.
Why designers use it
- Gate an enable line so a function only runs when both 'power good' and 'system ready' are true.
- Mask a clock signal so a counter only advances when an external trigger is asserted.
- Combine multiple end-of-conversion flags from parallel ADC channels into a single 'all done' signal.
- Build a chip-select decoder where address bits must all match a hard-wired pattern.
Best for
- Enable gating
- Address decoding
- Clock masking
Key specifications
- Logic family: 74HC, 74LV, 74AUP, 74AHCT
- Supply: 1.65 V – 5.5 V
- Propagation delay: 2 ns – 10 ns
- Drive strength: 4 – 24 mA
When not to use it
- When fan-in exceeds 4 — stack delay through series NMOS dominates and a CMOS NAND-NOR tree or look-up table is faster.
- For glue logic inside an FPGA — the AND function lives inside the LUT for free and a discrete IC just adds a board hop.
Common mistakes
- Floating an unused input pin — a CMOS AND with one input drifting will toggle on noise; tie unused inputs to Vₒₒ (since the AND identity is 1).
- Forgetting that the propagation delay is asymmetric: a 1→0 transition is slower than 0→1 because the series NMOS pull-down has to discharge the internal node before the inverter can flip.
Where you will find it
- A washing-machine controller uses a 74HC08 to gate the 'start motor' line: the motor only spins when the door-closed switch AND the water-level-OK sensor are both asserted, hardware-enforcing a safety interlock that no firmware bug can override.
- An automotive airbag controller uses an AND gate as the final arbiter on the squib firing line: only when both the crash accelerometer threshold AND the safing sensor have triggered does the firing capacitor dump into the squib, preventing accidental deployment from a single false sensor.
- A nuclear-physics coincidence detector uses fast AND gates to identify particle showers: when two adjacent scintillator detectors both register an event within a 5 ns window, the AND output triggers the data-acquisition system to record the event — the same two-detector coincidence trick Walter Bothe used in 1924.
A short history
An AND gate is a digital logic device with two or more inputs and one output. Its output is logic 1 only when all inputs are at logic 1; if any input is logic 0, the output is 0. This behavior is described by a truth table, and AND gates serve as building blocks within larger combinational logic circuits.
Good to know
- AND gates output high only when every input is high — the boolean intersection. Most ICs offer 2-input or 3-input versions.
- A 74HC08 packs four 2-input AND gates into a 14-pin DIP; the same die layout has been in production since 1982.
- Single-gate 'little logic' parts (SC-70-5) replace whole 14-pin DIPs in modern miniaturised gear, saving 10× the board area.