Ethernet PHY
Encodes/decodes MLT-3 (100BASE-TX) or PAM-5 (1000BASE-T) line codes, drives the magnetics with a precisely shaped pulse, and runs auto-negotiation with the far end to select speed, duplex, and master/slave clocking.
A digital-to-analog converter shapes line pulses through a baseband filter into the magnetics, which couple onto the four twisted pairs at ±2.5 V (1000BASE-T). On reception, an analog front-end slices the symbols, an adaptive equaliser removes pair-to-pair NEXT and FEXT crosstalk, and a digital signal processor recovers a 125 MHz symbol clock from the data using a clock-data recovery PLL. Auto-negotiation runs at 16 ns 'fast link pulses' to advertise capabilities before the link comes up.
In plain terms
Like a translator at the UN: the MAC speaks its own clean parallel dialect, and the PHY whispers it into the noisy multilingual cable in whatever encoding the far end happens to use.
Why designers use it
- Universal IEEE 802.3 compliance — every router, switch, IP camera, and embedded gateway uses the same PHY architecture for guaranteed interoperability.
- Cable-length tolerance — a 1000BASE-T PHY's adaptive equaliser keeps a 100 m Cat-5e link healthy even with crosstalk and shifted impedance.
- EEE (Energy-Efficient Ethernet, IEEE 802.3az) — modern PHYs sleep sub-circuits during idle traffic, saving milliwatts on always-on routers.
- Auto-MDIX — the PHY internally swaps RX/TX pair polarity and order so straight-through and crossover cables both work.
Best for
- Switch ports
- Embedded gateways
- IP cameras
Key specifications
- Speed: 10 / 100 / 1000 / 2,500 / 10,000 Mb/s
- Cable: Cat 5e – Cat 6A
- Distance: Up to 100 m on copper
- Interface to MAC: MII / RMII / RGMII / SGMII
- Supply: 1.0 V core + 3.3 V I/O
When not to use it
- Inside an SoC that already integrates a PHY — adding an external one duplicates power and PCB space.
- For 10G+ links — 10GBASE-T PHYs are far more complex (DSP-heavy, hot); use SFP+/QSFP modules with a separate framer instead.
Common mistakes
- Skipping the centre-tap bypass capacitors on the magnetics — the PHY's common-mode rejection collapses and the link fails BER tests at 100 m.
- Letting the RGMII clock skew drift past ±500 ps — the MAC and PHY hand-shake at 1000 Mb/s but bit-error rates spike whenever the chassis warms up.
Where you will find it
- A Ubiquiti EdgeRouter Lite uses a Marvell 88E1512 1000BASE-T PHY between its Cavium Octeon CPU and each RJ-45: the chip's integrated SmartEEE feature drops idle-port power by ~75 % so the box's 5 V supply stays cool inside a tight wall-mount enclosure.
- A Raspberry Pi 4B's Microchip LAN7515 USB-to-Ethernet PHY converts the SoC's USB 3.0 output to gigabit copper through a Bourns SM91501EL magnetic: the PHY's wake-on-LAN MagicPacket detector keeps the Pi reachable from a sleeping host without touching the CPU.
- An Axis P3245 IP camera uses a Realtek RTL8211F PHY to feed its H.265 video onto the network through a PoE+ powered link: the PHY's automatic master/slave negotiation lets one cable carry 30 W of power and 1 Gb/s of video through a building's existing structured cabling.
A short history
An Ethernet PHY provides the physical-layer connection between digital Ethernet circuitry and its transmission medium. A typical PHY has an interface to the media access controller and a medium-dependent interface toward the cable. Some support multiple rates and auto-negotiation, letting a device establish a compatible link with its partner.
Good to know
- Gigabit Ethernet on Cat 5e uses all four pairs simultaneously, transmitting and receiving on each pair via hybrid couplers — the magic of full-duplex on twisted-pair copper.
- An Ethernet PHY auto-negotiates speed and duplex mode at link-up — the 'pulse-burst' you can sometimes see on a scope when plugging in a cable.
- 1000BASE-T uses 4D-PAM5 line coding (5 amplitude levels per pair, with a 4-D Trellis code) to squeeze 1 Gb/s out of 100 m of unshielded twisted-pair.