ESD Array
An ESD-protection array packs four to eight low-capacitance TVS diodes into one tiny SOT-23-type package, ready to clamp ESD events (typically rated to IEC 61000-4-2 ±8 kV contact / ±15 kV air) on USB, HDMI, Ethernet, or button-pad lines. Examples: USBLC6 (USB), TPD4S012 (HDMI), and SP3010-04UTG (general 4-channel).
Each protected line ties to a pair of fast steering diodes whose cathodes/anodes meet at a central TVS or to Vₒₒ and GND rails. During normal operation the diodes are off and contribute only a small leakage and capacitance (typically <1 pF). When an ESD strike pushes a line beyond Vₒₒ or below GND, the steering diode forward-biases in nanoseconds, dumping the surge into the central TVS or supply rail where it's safely shunted.
In plain terms
A row of one-way pressure-relief valves on a manifold: as long as the pressure stays normal, the valves do nothing; the moment a spike arrives, every channel vents instantly and harmlessly.
Why designers use it
- Add ESD survival to every USB-C connector exposed to fingertips and cables.
- Protect the 4 differential pairs of a 1000Base-T Ethernet PHY without adding capacitance that breaks return loss.
- Clamp electrostatic discharges arriving on a tiny capacitive-touch button pad through the user's finger.
- Save the BOM cost of separate TVS diodes on every line of a multi-pin connector (one ESD array replaces 8 discretes).
Best for
- USB/HDMI ESD
- Ethernet PHY
- Touch buttons
Key specifications
- Working voltage: 3.3 V – 24 V per line
- Channels: 1 – 8 lines
- Capacitance: 0.5 pF – 50 pF
- ESD HBM: ±8 kV – ±30 kV
- Clamp voltage: +10 % – +50 % above working
When not to use it
- When the selected part is not rated for the relevant surge, sustained overvoltage or electrical-overstress condition.
- When its capacitance or layout degrades the actual interface's signal integrity. There is no universal data-rate cutoff for every ESD array.
Common mistakes
- Placing the ESD array several centimetres from the connector with traces running past sensitive ICs — the surge couples capacitively into nearby silicon before reaching the array.
- Choosing a low-capacitance array (0.3 pF) and routing it on long traces, where trace inductance dominates and the clamp lags the strike anyway.
Where you will find it
- A laptop's USB-C port uses a TI TPD8S300 8-channel ESD array immediately at the connector: every contact is clamped within 1 ns of any ±15 kV air-discharge event, sparing the downstream SuperSpeed re-driver and CC-line PD controller from damage when a user yanks a cable on a dry winter day.
- A car infotainment's HDMI output uses an STMicroelectronics HSP051-4M10 ESD array between the SoC and the HDMI connector: the part adds only 0.65 pF per pair, preserving 2.97 Gbit/s eye-quality while letting the system survive the IEC 61000-4-2 ±8 kV gun-test that car-OEM EMC labs perform.
- A baby-monitor's microphone-button board uses an SP0503BAHT three-channel ESD array on its tactile dome inputs: the tiny SOT-23-type part survives a finger-tip ESD strike that's released as the parent presses the button, preventing the MCU from latching up and resetting the device mid-feed.
A short history
An ESD protection array places transient-suppression elements at vulnerable circuit connections. They conduct during a voltage transient to divert surge current and limit the voltage reaching the protected circuit. Protection depends on the device and circuit design; the array is not a guarantee that every static discharge will be harmless.
Good to know
- An ESD protection array is part of a current path, not a force field around an IC. Package and PCB parasitics still matter.
- Select protection against the actual signal voltage, capacitance budget, clamping behavior and required test conditions rather than assuming all ESD events have the same energy.