DP Retimer
Per-lane, recovers the embedded clock from the 8b/10b or 128b/132b stream with a CDR PLL, decodes and re-encodes the data, and drives a fresh signal with full eye, full swing, and reset jitter budget.
Each lane has an analog front-end with a CTLE and DFE that opens the eye, then a clock-data recovery PLL locks to the symbol clock. The recovered bits go through a re-encoder that reasserts the link's running disparity, scrambling, and aux-channel multiplexing. Outputs use programmable de-emphasis and swing to launch a clean eye on the next segment. The retimer also forwards the AUX channel and the HPD line transparently.
In plain terms
Like a courier picking up a smudged letter, copying it cleanly onto fresh paper, and continuing the relay — the message is the same but the next handler doesn't inherit the smudge.
Why designers use it
- Reset the jitter budget — each retimer hop is allowed up to 0.3 UI of total jitter independent of upstream noise, so two retimers in series carry a 20 m link that one redriver couldn't.
- Support DP 2.0 UHBR rates (10/13.5/20 Gb/s) — at those rates, CDR-based regeneration is mandatory; redrivers can't reach.
- Transparent to LT-tunable PHY — the retimer participates in DisplayPort link training so the source still tunes its TX equalisation to the sink, not just to the retimer.
- Power efficiency — a retimer can sleep most of its analog when no traffic is detected on the link, dropping idle current under 50 mW.
Best for
- Active cables
- Docking stations
- Long PCB traces
Key specifications
- Operating limits: Check the exact manufacturer's datasheet (A family name does not establish voltage, current, temperature or timing limits.)
- Pin assignment: Match the complete part and package code (A similar name or function does not guarantee the same wiring.)
- Mechanical fit: Use the exact package drawing (Check pad layout, dimensions and viewing direction before building.)
When not to use it
- For short links under 1 m where loss is low — a redriver or even a passive trace is cheaper, lower-power, and adds no latency.
- Where strict zero-latency is required (some VR headsets) — the retimer's PLL adds 5–10 ns; a redriver or pure repeater is faster.
Common mistakes
- Mis-strapping the retimer's lane-rate detect pins so the CDR is configured for HBR3 (8.1 Gb/s) when the source actually negotiates UHBR10 — link training fails because the retimer drops symbols.
- Forgetting to forward the AUX channel — the retimer's main lanes work but link training fails because the sink can't reach the source's DPCD registers.
Where you will find it
- Apple's 6 m Thunderbolt 4 Pro cable uses Intel JHL8440 retimers at each end to maintain 40 Gb/s and 5K-60 Hz over twin-axial copper: the retimer's CDR-based regeneration is what lets the cable be 'active' rather than passive, hitting eye-mask compliance at the destination connector.
- A Dell WD22TB4 Thunderbolt 4 dock uses a Parade PS192 DisplayPort 1.4 retimer between its TBT4 host controller and its dual DP++ outputs: the retimer reopens the eye after the dock's internal traces and connectors, supporting 8K-30 Hz on the display output that a redriver alone couldn't sustain.
- Lenovo's ThinkPad X1 Carbon Gen 11 lid uses a Texas Instruments DP159 retimer between the SoC and the eDP panel: the retimer's CDR resets jitter accumulated through the hinge cable's flex transitions, so the OLED panel's timing controller sees a clean eye even when the lid is repeatedly opened to its maximum angle.
A short history
DisplayPort was standardised by VESA in 2006 to replace DVI and VGA with a royalty-free digital display interface. At link rates above 5.4 Gbit/s per lane (DisplayPort 1.3 and later), cable and board-trace losses require active retimer or redriver ICs to reshape the eye diagram before the sink device can reliably recover the clock and data. Texas Instruments, Parade Technologies, and Analogix were early suppliers of DisplayPort retimer ICs integrating equalisation, clock-data recovery, and re-serialisation. Retimers are now standard in docking stations, cables, and host SoCs supporting DisplayPort 2.0 at 20 Gbit/s per lane.